The entire handling of the modulation via OUT pin and the management of the transmission and reception’s frame were implemented by reconfiguring the internal FPGA of the programmer.
By implementing the software of the algorithm, the user has the possibility to program the EEPROM area including the SIGNAL PATH zone, either the NVRAM register which includes all the configurations (lock of the device included). It is also present a dedicated command which controls the LOCK status bit as for production and qualification tests it is mandatory to set the LOCK bit after final adjustment and programming.
In the end, the WriteNow! GUI allows you to load directly the file format generated by the application of Micronas configuration, easing the integration of the product further.